The present invention relates to the packaging of integrated circuits (ICs) and more particularly to a method of forming a stacked die package.
There is a continuing demand for speed and miniaturization in the electronics industry that drives assembly and packaging technology. Thus, packaging technology has turned to 3-D packages. 3-D packaging technologies include stacked die, stacked packages, folded package assemblies, and combinations of these options. Stacked die allows suppliers to rapidly develop basic multiple-die combinations. Often, two or more die are encased in a single fine-pitch ball grid array (BGA) package outline. Stacked packages offer a high-density packaging scheme that helps reduce package footprint. Unfortunately, such stacked die packages are relatively thick.
Another way to reduce package size is to modify the way in which integrated circuits are connected to each other. One method, called redistributed chip package (RCP) is to use photolithography and copper-plating steps to create chip-to-chip interconnects. The RCP approach begins by separating each die within an IC and placing the individual die in wafer-sized panel. Epoxy and molding compound are applied to the die, connection patterns are lithographically defined, vias are etched through a dielectric to the chip's I/O pads and copper interconnects are electroplated. RCP techniques can be used to define either land grid arrays or C5 balls to link the die to a substrate of a larger system, for example, a cell phone.
It would be advantageous to be able to provide a thin, stacked die package in order to further shrink the size of electronic devices.